The dimensions of semiconductor device features relentlessly plunge into the deep sub-micron range, as in the decananometer range, challenging conventional fabrication techniques. As critical dimensions shrink, it becomes increasingly more difficult to achieve high dimensional accuracy in an efficient manner with high manufacturing throughput. The minimum feature size depends upon the chemical and optical limits of a particular lithography system, and the tolerance for distortions of the shape. In addition to the limitations of conventional lithography, the manufacturing costs attendant upon accurately forming ultrafine design features increase, thereby requiring advances in processing designed for efficient use of facilities and high manufacturing throughput.
Double exposure techniques that involve spacer lithographic processes have evolved. However, these techniques have not been completely successful and suffer from low manufacturing throughput, some techniques requiring the use of various tools and frequent chemical mechanical polishing (CMP). Transportation of a wafer from one tool to another and frequent use of CMP are not only time consuming but inevitably results in reduced yield thereby placing a chip maker at a disadvantage. In today's competitive market, a yield of at least 70% is required for profitability.
Accordingly, a need exists for methodology enabling the fabrication of semiconductor chips comprising devices having accurately formed features in the deep sub-micron range, such as design features less than 35 nm, including design features less than 20 nm, e.g., less than 10 nm. There exists a particular need for such methodology enabling the accurate formation of ultrafine design features with high efficiency and high manufacturing throughput.